Performance and Energy Trade-offs of Bitline Isolation in Nanoscale CMOS Caches

High-performance cache architectures always pull up the bitlines in all cache subarrays to hide the bitline charging latency prior to a cache access. Unfortunately, such architectures lead to significant bitline discharge in unaccessed subarrays in nanoscale CMOS caches and waste power. Recent proposals advocate bitline isolation to reduce bitline discharge in unaccessed subarrays by turning off precharge devices located between the supply voltage and bitlines in these subarrays. Many of these proposals tacitly assume that on-demand precharging of isolated bitlines can be overlapped with address decoding and hidden from the cache access latency. Moreover, they assume that the energy overhead of switching precharge devices is insignificant. In this paper, we carefully investigate the performance and energy impact of bitline isolation and show that these tacit assumptions are not true in the following senses: (1) Precharging isolated bitlines cannot be overlapped with address decoding and lies on the cache access critical path in both current and future CMOS technologies. Therefore, early precharging is necessary for isolated bitlines to avoid prohibitively impacting cache access latency. (2) The energy overhead of switching the precharge devices in current (i.e., 130nm) CMOS technologies is prohibitively high and nearly offsets the bitline isolation’s energy saving. Fortunately, the switching overhead decreases with decreasing feature sizes because the precharging devices and bitlines tend to shrink for smaller feature sizes.